N-Channel: SMSLS844-04 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET same as Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 SOIC8 Linear Integrated Systems LS844 manufactured by Semiconix Semiconductor - Gold chip technology for known good N-Channel die, N-Channel flip chip, N-Channel die, wafer foundry for discrete semiconductors, integrated circuits and integrated passive components from Semiconix Semiconductor N-Channel: SMSLS844-04 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET same as Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 SOIC8 Linear Integrated Systems LS844 manufactured by Semiconix Semiconductor - Gold chip technology for known good N-Channel die, N-Channel flip chip, N-Channel die, wafer foundry for discrete semiconductors, integrated circuits and integrated passive components manufactured by Semiconix Semiconductor. Gold metallization for interconnections instead of aluminum or copper, for high reliability devices for system in package applications using silicon printed circuit boards, ceramic substrates or chip on board, assembled via flip chip or chip and wire. SOIC8 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844,SMSLS844-04,Dual,,N-Channel, gold,chip,goldchip,gold chip technology, known good die, flip chip, bare die, wafer foundry, discrete semiconductors, integrated circuits, integrated passive components,gold metallization, aluminum, copper, system in package, SIP, silicon printed circuit board, silicon PCB, ceramic substrates, chip on board, flip chip, chip and gold wire N-Channel: SMSLS844-04 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET same as Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 SOIC8 Linear Integrated Systems LS844 manufactured by Semiconix Semiconductor - Gold chip technology for known good N-Channel die, N-Channel flip chip, N-Channel die, wafer foundry for discrete semiconductors, integrated circuits and integrated passive components from Semiconix Semiconductor N-Channel: SMSLS844-04 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET same as Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 SOIC8 Linear Integrated Systems LS844 manufactured by Semiconix Semiconductor - Gold chip technology for known good N-Channel die, N-Channel flip chip, N-Channel die, wafer foundry for discrete semiconductors, integrated circuits and integrated passive components manufactured by Semiconix Semiconductor. Gold metallization for interconnections instead of aluminum or copper, for high reliability devices for system in package applications using silicon printed circuit boards, ceramic substrates or chip on board, assembled via flip chip or chip and wire. SOIC8 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844,SMSLS844-04,Dual,,N-Channel, gold,chip,goldchip,gold chip technology, known good die, flip chip, bare die, wafer foundry, discrete semiconductors, integrated circuits, integrated passive components,gold metallization, aluminum, copper, system in package, SIP, silicon printed circuit board, silicon PCB, ceramic substrates, chip on board, flip chip, chip and gold wire REGISTER-LOGIN PRODUCTS CROSS REFERENCE INVENTORY REQUEST QUOTE ORDER ONLINE SITE MAP semiconix semiconductor - where the future is today - gold chip technology SMSLS844-04 - nanoDFN GOLD CHIP TECHNOLOGY™ SOIC8 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET FEATURES APPLICATIONS N-Channel JFET Transistor - nDFN High input impedance High Gain High transconductance Low noise Low value of gate to drain capacitance High reliability nanoDFN package Unique 10mils thin design Gold over nickel metallization RoHS compliant, Lead Free Compatible with surface mount, chip and wire and flip chip assembly process. Available packaged in SOIC8 High Input Impedance Amplifier Low-Noise Amplifier Differential Amplifier Constant Current Source Analog Switch or Gate Voltage Controlled Resistor Instrumentation, medical and sensor applications Chip on Board System in package SIP Hybrid Circuits SMSLS844-04 LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET - PRODUCT DESCRIPTION The junction field effect transistor in its simplest form is essentially a voltage controlled resistor. The resistive element is usually a bar of silicon. For an N-channel JFET this bar is an N-type material sandwiched between two layers of P-type material. The two layers of P-type material are electrically connected together and are called the gate. One end of the N-type bar is called the source and the other is called the drain. Current is injected into the channel from the source terminal, and collected at the drain terminal. The interface region of the P- and the N-type materials forms a P-N junction. Since the Gate junction is reverse biased and because there is no minority carrier contribution to the flow through the device, the input impedance is extremely high. The control element for the JFET comes from depletion of charge carriers from the n-channel. When the Gate is made more negative, it depletes the majority carriers from a larger depletion zone around the gate. This reduces the current flow for a given value of Source-to-Drain voltage. Modulating the Gate voltage modulates the current flow through the device. Semiconix N-Channel JFET Transistors series are available in very thin 0201 nanoDFN package. These products are ideal for surface mount, hybrid circuits and multi chip module applications. HIGH RELIABILITY BARE DIE AND SYSTEM IN PACKAGE - SHORT APPLICATION NOTE COB (Chip on Board) and SiP (System-in-Package) are integrating proven mature products in bare die of mixed technologies i.e. Si, GaAs, GaN, InP, passive components, etc that cannot be easily implemented in SOC (System-on-Chip) technology. COB and SiP have small size footprint, high density, shorter design cycle time, easier to redesign and rework, use simpler and less expensive assembly process. For extreme applications the bare die has to withstand also harsh environmental conditions without the protection of a package. KGD, Known Good Die concept is no longer satisfactory if the die cannot withstand harsh environmental conditions and degrades. Standard semiconductor devices supplied by many manufacturers in bare die are build with exposed aluminum pads that are extremely sensitive to moisture and corrosive components of the atmosphere. Semiconix has reengineered industry standard products and now offers known good die for bare die applications with gold interconnection and well-engineered materials that further enhance the die reliability. Semiconix also offers Silicon Printed Circuit Board technology with integrated passive components as a complete high reliability SIP solution for medical, military and space applications. See AN-SMX-001 DISCRETE SEMICONDUCTORS MANUFACTURING PROCESS Discrete semiconductors are manufactured using Semiconix in house high reliability semiconductor manufacturing processes. All semiconductor devices employ precision doping via ion implantation, silicon nitride junction passivation, platinum silicided contacts and gold interconnect metallization for best performance and reliability. MNOS capacitors, Tantalum Nitride TaN or Sichrome SiCr thin film resistors are easily integrated with discrete semiconductors on same chip to obtain standard and custom complex discrete device solutions. ABSOLUTE MAXIMUM RATINGS @ 25 °C (unless otherwise stated) Parameter Symbol Value Unit Storage Temperature TSTG -65 to +150 °C Operating Junction Temperature TJ -55 to +150 °C Power Dissipation PD 400 mW Gate Forward Current -Igf 50 mA Gate to Drain or Source Voltage -VGSS 60 V Drain to Source Voltage -VDSO 60 V Electrical Characteristics* TC = 25°C unless otherwise noted Name Symbol Test Conditions Value Unit Min. Typ. Max Drift vs. Temperature |ΔVGS1-2/ΔT|max. VDG=10V, ID=500mA,TA=-55°C to +125°C 10 mV/°C Offset Voltage |VGS1-2|max. VDG=10V, ID=500mA 5 mV Breakdown Voltage BVGSS VDS=0 ID=1nA 60 V Gate-to-Gate Breakdown BVGGO IG=1nA ID=0 IS=0 60 V Transconductance Mismatch |Yfs1-2/Yfs| VDG=15V ID=500mA 1 5 % Drain Current Full Conduction IΔSS VDS=15V,VGS=0 1.5 5 15 mA Drain Current,Mismatch at Full Conduction |IΔSS1-2/IΔSS| VDG=10V VGS=0 1 5 % Gate Voltage,Pinchoff VGS(off)orVP VDS=15V ID=1nA 1 3.5 V Gate Voltage,Operating Range VGS VDS=15V ID=500mA 0.5 3.5 V Gate Current Operating -IG VDG=15V ID=500mA 16 60 pA Gate Current Operating -IG VDG=15V ID=500mA TA=+125°C 50 nA Gate Current,High Temperature -IG VDG=3V ID=500mA 5 30 pA Gate Current,At Full Conduction -IGSS VDG=15V,VDS=0V 100 pA Transconductance Full Conduction Yfss VDG=10V VGS=0 f=1kHz 1500 mmho Transconductance Typical Operation Yfs VDG=15V ID=500mA 1000 1500 mmho Output Conductance,Full Operation YOSS VDG=15V,VGS=0 20 mmho Output Conductance, Operating YOS VDG=15V,ID=500mA 0.2 2 mmho Output Conductance, Differential |YOS1-2| VDG=15V,ID=500mA 0.02 0.2 mmho Common Mode Rejection,-20 log |DVGS1-2/DVDS| CMR DVDS=10to 20V, ID=500mA 90 110 dB Common Mode Rejection,-20 log |DVGS1-2/DVDS| CMR DVDS=5 to 10V, ID=500mA 85 dB Common Source Input Capacitance Ciss VDS=15V,ID=500mA,f=1MHz 8 pF Reverse Transfer capacitance Crss VDS=15V,ID=500mA,f=1MHz 3 pF Drain to Drain Capacitance CΔΔ VDG=15V,ID=500mA 0.5 pF Noise Figure NF VDS=15V,VGS=0,RG=10MW,f=100Hz,NBW=6Hz 0.5 dB Equivalent Input Noise Voltage en VDS=15V,ID=500mA,f=1kHz 7 nV/√Hz Equivalent Input Noise Voltage en VDS=15V,ID=500mA,f=10Hz 11 nV/√Hz 1. These ratings are limiting values above which the serviceability of any semiconductor may be impaired. SPICE MODEL Spice model pending. CROSS REFERENCE PARTS: Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 GENERAL DIE INFORMATION Substrate Thickness [mils] Package size Pads dimensions per drawing Backside Silicon 10±2 1.02x0.51mm [40x20mils] Gold Tin, Ni/Au, 5µm±1 thickness, solder reflow assembly Optional backside coating and/or marking. LAYOUT / DIMENSIONS / PAD LOCATIONS SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET nanoDFN 4 leads SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET Package pinout: 1 - G1,2 - D1,3 - S1,4 - G2,5 - D2,6 - S2, SOIC8 Package pinout Pin # Function 1 S1 2 D1 3 SS 4 G1 5 S2 6 D2 7 SS 8 G2 SOIC8 SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET nanoDFN SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET SEMICONDUCTOR ASSEMBLY PROCESS - SHORT APPLICATION NOTE SMX-nDFN - NanoDFN package is a very thin (10mils) proprietary wafer level chip size package W-CSP technology developed by Semiconix. SMX-nDFN is the most efficient wafer level chip size package W-CSP designed for mixed surface mount and flip chip applications. The assembly process is same as for packaged surface mount components. The process consist of at least 3 steps; -screen print solder paste on the printed circuit board; -flip chip, align and attach to the tacky solder paste; -dry paste, reflow at >220°C, clean, etc. SMX-nDFN packages can also be attached with conductive silver epoxy in low temperature applications. The assembly process is also very simple and inexpensive consisting of 3 steps: - transfer a thin conductive epoxy layer onto the bonding pads; -align to substrate and attach; -cure silver epoxy and inspect. SMX-nDFN packages are available in many sizes with landing pads compatible with the industry standard CSP as well as many surface mount packages. STANDARD PRODUCTS ORDERING INFORMATION VERSION SMX P/N WAFFLE PACKS QUANTITY U/P($) TAPE / REEL MIN QUANTITY U/P($) nDFN-4 SMSLS844-04-nDFN-4 -WP 10000 -TR 19000 nDFN-4 SMSLS844-04-nDFN-4 -WP 50000 -TR 95000 SOIC8 SMSLS844-04-SOIC8 -WP 1000 -TR 95000 PRICES - Listed prices are only for standard products, available from stock. Inventory is periodically updated. List prices for other quantities and tolerances are available on line through Instant Quote. For standard products available from stock, there is a minimum line item order of $550.00. No rights can be derived from pricing information provided on this website. Such information is indicative only, for budgetary use only and subject to change by SEMICONIX SEMICONDUCTOR at any time and without notice. LEAD TIMES - Typical delivery for standard products is 4-6 weeks ARO. For custom devices consult factory for an update on minim orders and lead times. CONTINOUS SUPPLY - Semiconix guarantees continuous supply and availability of any of its standard products provided minimum order quantities are met. CUSTOM PRODUCTS - For custom products sold as tested, bare die or known good die KGD, there will be a minimum order quantity MOQ. Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For high volume and pick and place applications, dice are also shipped on film frame -FF. For special die level KGD requirements, different packaging or custom configurations, contact sales via CONTACTS page. SAMPLES - Samples are available only for customers that have issued firm orders pending qualification of product in a particular application. ORDERING - Semiconix accepts only orders placed on line by registered customers. On line orders are verified, accepted and acknowledged by Semiconix sales department in writing. Accepted orders are non cancelable binding contracts. SHIPING - Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For high volume and pick and place applications, dice are also shipped on film frame -FF. INSTANT QUOTE Semiconix P/N Quantity E-mail DISCLAIMER - SEMICONIX has made every effort to have this information as accurate as possible. However, no responsibility is assumed by SEMICONIX for its use, nor for any infringements of rights of third parties, which may result from its use. SEMICONIX reserves the right to revise the content or modify its product line without prior notice. SEMICONIX products are not authorized for and should not be used within support systems, which are intended for surgical implants into the body, to support or sustain life, in aircraft, space equipment, submarine, or nuclear facility applications without the specific written consent. HOME PRODUCT TREE PACKAGES PDF VERSION SEARCH SEMICONIX SEMICONDUCTOR www.semiconix-semiconductor.com Tel:(408)986-8026 Fax:(408)986-8027 SEMICONIX SEMICONDUCTOR Last updated:January 01, 1970 Display settings for best viewing: Current display settings: Page hits: 17 Screen resolution: 1124x864 Screen resolution: Total site visits: 315200 Color quality: 16 bit Color quality: bit 1990-2009 SEMICONIX SEMICONDUCTOR All rights reserved. No material from this site may be used or reproduced without permission.

REGISTER-LOGIN PRODUCTS CROSS REFERENCE INVENTORY REQUEST QUOTE ORDER ONLINE SITE MAP

   
semiconix semiconductor - where the future is today - gold chip technology SMSLS844-04 - nanoDFN
GOLD CHIP TECHNOLOGY™ SOIC8 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET

FEATURES APPLICATIONS N-Channel JFET Transistor - nDFN
High input impedance
High Gain
High transconductance
Low noise
Low value of gate to drain capacitance
High reliability nanoDFN package
Unique 10mils thin design
Gold over nickel metallization
RoHS compliant, Lead Free
Compatible with surface mount, chip and wire and flip chip assembly process.
Available packaged in SOIC8
High Input Impedance Amplifier
Low-Noise Amplifier
Differential Amplifier
Constant Current Source
Analog Switch or Gate
Voltage Controlled Resistor
Instrumentation, medical and sensor applications
Chip on Board
System in package SIP
Hybrid Circuits
SMSLS844-04 LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET
SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET

LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET - PRODUCT DESCRIPTION
The junction field effect transistor in its simplest form is essentially a voltage controlled resistor. The resistive element is usually a bar of silicon. For an N-channel JFET this bar is an N-type material sandwiched between two layers of P-type material. The two layers of P-type material are electrically connected together and are called the gate. One end of the N-type bar is called the source and the other is called the drain. Current is injected into the channel from the source terminal, and collected at the drain terminal. The interface region of the P- and the N-type materials forms a P-N junction. Since the Gate junction is reverse biased and because there is no minority carrier contribution to the flow through the device, the input impedance is extremely high. The control element for the JFET comes from depletion of charge carriers from the n-channel. When the Gate is made more negative, it depletes the majority carriers from a larger depletion zone around the gate. This reduces the current flow for a given value of Source-to-Drain voltage. Modulating the Gate voltage modulates the current flow through the device.
Semiconix N-Channel JFET Transistors series are available in very thin 0201 nanoDFN package.
These products are ideal for surface mount, hybrid circuits and multi chip module applications.

HIGH RELIABILITY BARE DIE AND SYSTEM IN PACKAGE - SHORT APPLICATION NOTE
COB (Chip on Board) and SiP (System-in-Package) are integrating proven mature products in bare die of mixed technologies i.e. Si, GaAs, GaN, InP, passive components, etc that cannot be easily implemented in SOC (System-on-Chip) technology. COB and SiP have small size footprint, high density, shorter design cycle time, easier to redesign and rework, use simpler and less expensive assembly process. For extreme applications the bare die has to withstand also harsh environmental conditions without the protection of a package. KGD, Known Good Die concept is no longer satisfactory if the die cannot withstand harsh environmental conditions and degrades. Standard semiconductor devices supplied by many manufacturers in bare die are build with exposed aluminum pads that are extremely sensitive to moisture and corrosive components of the atmosphere. Semiconix has reengineered industry standard products and now offers known good die for bare die applications with gold interconnection and well-engineered materials that further enhance the die reliability. Semiconix also offers Silicon Printed Circuit Board technology with integrated passive components as a complete high reliability SIP solution for medical, military and space applications. See AN-SMX-001

DISCRETE SEMICONDUCTORS MANUFACTURING PROCESS
Discrete semiconductors are manufactured using Semiconix in house high reliability semiconductor manufacturing processes. All semiconductor devices employ precision doping via ion implantation, silicon nitride junction passivation, platinum silicided contacts and gold interconnect metallization for best performance and reliability. MNOS capacitors, Tantalum Nitride TaN or Sichrome SiCr thin film resistors are easily integrated with discrete semiconductors on same chip to obtain standard and custom complex discrete device solutions.

ABSOLUTE MAXIMUM RATINGS @ 25 °C (unless otherwise stated)
Parameter Symbol Value Unit
Storage Temperature TSTG -65 to +150 °C
Operating Junction Temperature TJ -55 to +150 °C
Power Dissipation PD 400 mW
Gate Forward Current -Igf 50 mA
Gate to Drain or Source Voltage -VGSS 60 V
Drain to Source Voltage -VDSO 60 V

Electrical Characteristics* TC = 25°C unless otherwise noted
Name Symbol Test Conditions Value Unit
Min. Typ. Max
Drift vs. Temperature |ΔVGS1-2/ΔT|max. VDG=10V, ID=500mA,TA=-55°C to +125°C 10 mV/°C
Offset Voltage |VGS1-2|max. VDG=10V, ID=500mA 5 mV
Breakdown Voltage BVGSS VDS=0 ID=1nA 60 V
Gate-to-Gate Breakdown BVGGO IG=1nA ID=0 IS=0 60 V
Transconductance Mismatch |Yfs1-2/Yfs| VDG=15V ID=500mA 1 5 %
Drain Current Full Conduction IΔSS VDS=15V,VGS=0 1.5 5 15 mA
Drain Current,Mismatch at Full Conduction |IΔSS1-2/IΔSS| VDG=10V VGS=0 1 5 %
Gate Voltage,Pinchoff VGS(off)orVP VDS=15V ID=1nA 1 3.5 V
Gate Voltage,Operating Range VGS VDS=15V ID=500mA 0.5 3.5 V
Gate Current Operating -IG VDG=15V ID=500mA 16 60 pA
Gate Current Operating -IG VDG=15V ID=500mA TA=+125°C 50 nA
Gate Current,High Temperature -IG VDG=3V ID=500mA 5 30 pA
Gate Current,At Full Conduction -IGSS VDG=15V,VDS=0V 100 pA
Transconductance Full Conduction Yfss VDG=10V VGS=0 f=1kHz 1500 mmho
Transconductance Typical Operation Yfs VDG=15V ID=500mA 1000 1500 mmho
Output Conductance,Full Operation YOSS VDG=15V,VGS=0 20 mmho
Output Conductance, Operating YOS VDG=15V,ID=500mA 0.2 2 mmho
Output Conductance, Differential |YOS1-2| VDG=15V,ID=500mA 0.02 0.2 mmho
Common Mode Rejection,-20 log |DVGS1-2/DVDS| CMR DVDS=10to 20V, ID=500mA 90 110 dB
Common Mode Rejection,-20 log |DVGS1-2/DVDS| CMR DVDS=5 to 10V, ID=500mA 85 dB
Common Source Input Capacitance Ciss VDS=15V,ID=500mA,f=1MHz 8 pF
Reverse Transfer capacitance Crss VDS=15V,ID=500mA,f=1MHz 3 pF
Drain to Drain Capacitance CΔΔ VDG=15V,ID=500mA 0.5 pF
Noise Figure NF VDS=15V,VGS=0,RG=10MW,f=100Hz,NBW=6Hz 0.5 dB
Equivalent Input Noise Voltage en VDS=15V,ID=500mA,f=1kHz 7 nV/√Hz
Equivalent Input Noise Voltage en VDS=15V,ID=500mA,f=10Hz 11 nV/√Hz
1. These ratings are limiting values above which the serviceability of any semiconductor may be impaired.
SPICE MODEL
Spice model pending.
CROSS REFERENCE PARTS: Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844

GENERAL DIE INFORMATION
Substrate Thickness
[mils]
Package size Pads dimensions per drawing Backside
Silicon 10±2 1.02x0.51mm
[40x20mils]
Gold Tin, Ni/Au, 5µm±1 thickness, solder reflow assembly Optional backside coating and/or marking.

LAYOUT / DIMENSIONS / PAD LOCATIONS
SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET nanoDFN 4 leads SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET
Package pinout: 1 - G1,2 - D1,3 - S1,4 - G2,5 - D2,6 - S2,
SOIC8 Package pinout
Pin # Function
1 S1
2 D1
3 SS
4 G1
5 S2
6 D2
7 SS
8 G2
SOIC8 SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET
nanoDFN SMSLS844-04 Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844, Linear Integrated Systems LS844 Linear Integrated Systems LS844 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET

SEMICONDUCTOR ASSEMBLY PROCESS - SHORT APPLICATION NOTE
SMX-nDFN - NanoDFN package is a very thin (10mils) proprietary wafer level chip size package W-CSP technology developed by Semiconix.
SMX-nDFN is the most efficient wafer level chip size package W-CSP designed for mixed surface mount and flip chip applications. The assembly process is same as for packaged surface mount components. The process consist of at least 3 steps; -screen print solder paste on the printed circuit board; -flip chip, align and attach to the tacky solder paste; -dry paste, reflow at >220°C, clean, etc.
SMX-nDFN packages can also be attached with conductive silver epoxy in low temperature applications. The assembly process is also very simple and inexpensive consisting of 3 steps: - transfer a thin conductive epoxy layer onto the bonding pads; -align to substrate and attach; -cure silver epoxy and inspect. SMX-nDFN packages are available in many sizes with landing pads compatible with the industry standard CSP as well as many surface mount packages.

STANDARD PRODUCTS ORDERING INFORMATION

VERSION SMX P/N WAFFLE PACKS QUANTITY U/P($) TAPE / REEL MIN QUANTITY U/P($)
nDFN-4 SMSLS844-04-nDFN-4 -WP 10000 -TR 19000
nDFN-4 SMSLS844-04-nDFN-4 -WP 50000 -TR 95000
SOIC8 SMSLS844-04-SOIC8 -WP 1000 -TR 95000

PRICES - Listed prices are only for standard products, available from stock. Inventory is periodically updated. List prices for other quantities and tolerances are available on line through Instant Quote. For standard products available from stock, there is a minimum line item order of $550.00. No rights can be derived from pricing information provided on this website. Such information is indicative only, for budgetary use only and subject to change by SEMICONIX SEMICONDUCTOR at any time and without notice.
LEAD TIMES - Typical delivery for standard products is 4-6 weeks ARO. For custom devices consult factory for an update on minim orders and lead times.
CONTINOUS SUPPLY - Semiconix guarantees continuous supply and availability of any of its standard products provided minimum order quantities are met.
CUSTOM PRODUCTS - For custom products sold as tested, bare die or known good die KGD, there will be a minimum order quantity MOQ. Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For high volume and pick and place applications, dice are also shipped on film frame -FF. For special die level KGD requirements, different packaging or custom configurations, contact sales via CONTACTS page.
SAMPLES - Samples are available only for customers that have issued firm orders pending qualification of product in a particular application.
ORDERING - Semiconix accepts only orders placed on line by registered customers. On line orders are verified, accepted and acknowledged by Semiconix sales department in writing. Accepted orders are non cancelable binding contracts.
SHIPING - Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For high volume and pick and place applications, dice are also shipped on film frame -FF.

INSTANT QUOTE
Semiconix P/N Quantity E-mail    

DISCLAIMER - SEMICONIX has made every effort to have this information as accurate as possible. However, no responsibility is assumed by SEMICONIX for its use, nor for any infringements of rights of third parties, which may result from its use. SEMICONIX reserves the right to revise the content or modify its product line without prior notice. SEMICONIX products are not authorized for and should not be used within support systems, which are intended for surgical implants into the body, to support or sustain life, in aircraft, space equipment, submarine, or nuclear facility applications without the specific written consent.

HOME PRODUCT TREE PACKAGES PDF VERSION SEARCH

SEMICONIX SEMICONDUCTOR www.semiconix-semiconductor.com
Tel:(408)758-8694 Fax:(408)986-8027
SEMICONIX SEMICONDUCTOR
Last updated:July 06, 2009 Display settings for best viewing: Current display settings:
Page hits: Screen resolution: 1124x864 Screen resolution:
Total site visits: Color quality: 16 bit Color quality: bit
© 1990-2019 SEMICONIX SEMICONDUCTOR All rights reserved. No material from this site may be used or reproduced without permission.